FIG. 4 is a schematic diagram showing a configuration of a conventional semiconductor memory. The conventional semiconductor memory is designated by the general reference character 400, and can include a memory cell array 402, a sense amplifier 404, and a restore voltage control circuit 406. An external power supply voltage Vcc is also supplied to the semiconductor memory 400.
The memory cell array 402 can comprise a number of memory cells (not shown), each having an n-channel MOS transistor that can include a gate, a source, and a drain. The transistors can be arranged in a matrix and located at intersections between a plurality of word lines and a plurality of bit line pairs.
The sense amplifier 404 can not only read contents stored in a memory cell of the memory cell array 402, but can also restore the stored contents of the memory cell. The restore voltage control circuit 406 can supply a read voltage and a restore voltage to the sense amplifier 404.
The sense amplifier 404 can include p-channel metal-oxide-semiconductor (PMOS) transistors T400 and T402 that can be conceptualized as a differential pair; n-channel MOS (NMOS) transistors T404 and T406 that can be conceptualized as an active load; a PMOS transistor T408 that can control a connection between a common source signal line SAP and an external power supply Vcc; and an NMOS transistor T410 that can control a connection between a common source signal line SAN and an external power supply V.sub.SS.
The sense amplifier 404 can further include a connection node LI that can connect the drains of PMOS transistor T400 and NMOS transistor T404 to one another, and further to a bit line 408, and a connection node L2 that can connect the drains of PMOS transistors T402 and NMOS transistor T406 to one another, and further to a bit line 410. The gates of NMOS transistor T406 and PMOS transistor T402 can be coupled to connection node L1. The gates of NMOS transistor T404 and PMOS transistor T400 can be coupled to connection node L2.
Bit lines 408 and 410 can be connected to the current paths of NMOS transistors corresponding to the memory cells arranged in the memory cell array 402.
NMOS transistor T410 can have a drain connected to the common source signal line SAN, a source coupled to the Vss power supply ("grounded"), and a gate coupled to a sense signal SENSE through inverters 412-b and 412-c.
The common source signal line SAP can be connected to the external power supply Vcc through PMOS transistor T408. Transistor T408 can have a back gate (or "body") connected to its source and a gate that receives a switch signal SWITCH through an inverter 414. A switch signal SWITCH can be generated by a switch signal generating circuit (not shown).
The output of the restore voltage control circuit 406 can be connected to the common source signal line SAP through a PMOS transistor T412. Transistor T412 can have a back gate coupled to its source and a gate that receives the sense signal SENSE through inverter 412-a. The sense signal SENSE can be generated by a sense signal generating circuit (not shown).
The restore voltage control circuit 406 can include a comparator circuit 416 and a PMOS transistor T414. A reference voltage Vref, that is lower than the external supply voltage Vcc, can be supplied to the comparator circuit 416. The reference voltage Vref can be generated by a reference voltage generating circuit (not shown). PMOS transistor T414 can have a source connected to the external power supply Vcc, a drain connected to the input of comparator circuit 416 and a gate connected to the output of comparator circuit 416.
FIG. 5 is a timing diagram illustrating a restore operation of the conventional semiconductor memory of FIG. 4. At first, a "boot" voltage Vboot, that is higher than the external power supply voltage (Vcc) can be applied to a word line. The word line can correspond to the gate of an NMOS transistor of a memory cell on which a restore operation is to be performed. The response of a "booted" word line is shown by waveform 500.
The application of the Vboot voltage can result in the potential of the memory cell appearing on a bit line. The response of a bit line is shown by waveform 502. Waveform 504 illustrates the response of the other bit line of a bit line pair that includes the bit line illustrated by waveform 502. The level of the bit line illustrated by waveform 504 is shown to go to zero.
Based on the external power supply voltage Vcc and the reference voltage Vref, the restore voltage control circuit 406 can generate an internal voltage N.sub.INTS that can be equal to the reference voltage Vref. The sense signal SENSE can then transition high. This transition is shown by waveform 506. The high sense signal SENSE value can be inverted by inverter 412-a and applied to the gate of PMOS transistor T412. The high sense signal SENSE can be further driven by inverters 412-b and 412-c and applied to the gate of NMOS transistor T410. In this way, PMOS transistor T412 and NMOS transistor T410 can be placed in an "on" state. Thus, the internal voltage N.sub.INTS from the restore voltage control circuit 406 can be supplied to the common source signal line SAP of sense amplifier 404. This is illustrated by waveform 508 of FIG. 5.
When the internal voltage N.sub.INTS is supplied to the sense amplifier 404, sensing of the bit line levels by the sense amplifier 404 can start. A switch signal SWITCH can then transition high. The high switch signal SWITCH can be inverted by inverter 414 and applied to the gate of PMOS transistor T408, turning on transistor T408. As a result, the external power supply voltage Vcc can be supplied to the common source signal line SAP instead of the internal voltage V.sub.INTS. The sensing of the bit line level can thereby be accelerated as shown by waveforms 502 and 504. The storage contents of a memory cell (a "1" or a "0") can be read out according to the level sense states of the bit lines (shown by waveforms 502 and 504).
When the switch signal SWITCH returns low, PMOS transistor T408 can be turned off, terminating the supply of the external power supply voltage Vcc to the sense amplifier 404. Instead, the internal voltage N.sub.INTS is once again supplied to the sense amplifier 404. In this way, restoration of a data value, which has been accelerated by the external power supply voltage Vcc, can be completed with the internal voltage V.sub.INTS.
In recent years, semiconductor memory devices have included sense amplifiers and memory cell arrays that can operate at an internal voltage that is less than an external power supply voltage. Sense amplifiers and memory cell arrays of this type can have improved operating speeds, as the overall size of the device ("chip") can be scaled down by utilizing fine bit lines (bit lines with smaller line widths) and/or reductions in the threshold voltage of MOS transistors.
A drawback to such semiconductor memory devices having lower internal voltages, is that the restore voltage control circuit (such as that show as item 406 in FIG. 4) can be undesirable in such devices. The application of an external power supply voltage to reduced operating voltage sense amplifiers and/or memory cell arrays can result in "latch-up" or other adverse consequences.